1. Technical Field
The present invention relates in general to the field of application specific integrated circuits (ASICs) and in particular to latch circuits. Still more particularly, the present invention relates to an improved method and system for preventing current leakage in level sensitive scan design (LSSD) latch circuits.
2. Description of the Related Art
Application-specific integrated circuits (ASICs) are integrated circuits (ICs) that are customized for one or more particular uses. Latches include multiple logic gate circuits and are used to store information in asynchronous sequential logic systems. Since a single latch circuit can store one bit of information, multiple latches are typically utilized within an ASIC. As circuit geometries continue to get smaller, the power density of conventional ASICs is becoming prohibitively large.
In conventional ASICs, power is primarily consumed by active logic when signal values change. However, power can also be lost due to leakage from the source to drain. As circuit density increases, the ratio between the number of pins contacted by a circuit tester and the amount of random logic contained in a design decreases, thereby making it more difficult for manufacturing tests to discover manufacturing defects (e.g., stuck at 0 or stuck at 1).
In order to increase the observability and controllability of internal logic of circuit designs, designers often utilize level sensitive scan design (LSSD). LSSD provides points within an ASIC design where a tester can directly scan values during manufacturing test. After a circuit passes manufacturing test (i.e. in functional mode), the scan clocks are typically tied off from the scan logic portion of the LSSD latch. However, the scan logic portion of the latch is still typically connected to the power source of the ASIC, which allows the scan logic portion of the LSSD latch circuit to continue to leak current. Current leakage that occurs when the ASIC is in functional mode causes the scan logic portion of the LSSD latch circuit to consume additional energy and generate unnecessary heat. Since conventional ASICs may include millions of latches, even a small amount of current leakage in each latch can produce a large cumulative power loss. Consequently, an improved method for reducing power consumption by preventing current leakage in LS SD latch circuits is needed.